POWER DISTRIBUTION ON PRINTED CIRCUIT BOARDS
Bibliography

Robust Electronic Design, Inc.

John R. Barnes KS4GL, PE, NCE, NCT, ESDC Eng, ESDC Tech, PSE, SM IEEE
December 30, 2009
jrbarnes@iglou.com

Please note: renumbered references on June 18, 2009, because added over 600 documents since January (went from 1228 to 1848 items)!

We can ensure that our electronic circuits will operate consistently and reliably by:

A lack of Power Integrity can cause an electronic system to:

My first book, Electronics System Design: Interference and Noise Control Techniques (Prentice-Hall, Englewood Cliffs, NJ, 1987) discusses Power Integrity under analog and digital circuit design in:

My second and third books, Robust Electronic Design Reference Book, Volumes I and II, were published by Kluwer Academic Publishers (now part of Springer) in Mar. 2004. They discuss Power Integrity in great detail in:

BOOKS:

[1] Applications Guide to EMI, RFI, ESD Solutions. AVX.

[2] Design Guidelines for Electronic Packaging Utilizing High-Speed Techniques, IPC-D-317A. IPC, Northbrook, IL, 1995.

[3] Handbook of EC EMC Compliance. Boxborough, MA: Compliance Design, 1993.

[4] Handbook of EU EMC Compliance. Boxborough, MA: Compliance Design, 1995.

[5] Handbook of EU EMC Compliance. Boxborough, MA: Compliance Design, 1996.

[6] Practical Design Techniques for Power and Thermal Management . Norwood, MA: Analog Devices, 1998.

[7] Signal Integrity Issues in PCB Design. Bellevue, WA: UltraCAD Design, 2002.

[8] The Best of Analog Dialogue 1967 to 1991. Analog Devices, 1991.

[9] Unitrode Power Supply Design Seminar SEM-1100. Merrimack, NH: Unitrode, 1996.

[10] Unitrode Power Supply Design Seminar SEM-1200. Merrimack, NH: Unitrode, 1997.

[11] Archambeault, Bruce R., PCB Design for Real-World EMI Control . Kluwer Academic Publishers, Boston, 2002.

[12] Bakoglu, H. B., Circuits, Interconnections, and Packaging for VLSI. New York: Addison-Wesley, 1990.

[13] Barnes, John R., Electronics System Design: Interference and Noise Control Techniques. Prentice-Hall, Englewood Cliffs, NJ, 1987.

[14] Barnes, John R., Robust Electronic Design Reference Book, Volumes I and II. Kluwer Academic Publishers, Boston, 2004.

[15] Blankenhorn, James C., PCB Design of High-Speed Digital Circuits . Scotts Valley, CA: SMT Plus, 2002.

[16] Blood, Jr., William R., MECL System Design Handbook, 4th Edition . Motorola Semiconductor Products, 1983.

[17] Bogatin, Eric, Signal Integrity - Simplified. Upper Saddle River, NJ: Prentice-Hall, 2004.

[18] Brooks, Douglas, Signal Integrity Issues and Printed Circuit Board Design. Upper Saddle River, NJ: Prentice Hall PTR, 2003.

[19] Buchanan, James E., BiCMOS/CMOS Systems Design. McGraw-Hill, New York, 1991.

[20] Buchanan, James E., CMOS/TTL Digital Systems Design. McGraw-Hill, New York, 1990.

[21] Buchanan, James E., Signal and Power Integrity in Digital Systems: TTL, CMOS, and BiCMOS. McGraw-Hill, New York, 1996.

[22] Dally, William J., and Poulton, John W., Digital Systems Engineering, Cambridge University Press, Cambridge, UK, 1998.

[23] Deeley, Paul McKnight, Electrolytic Capacitors. Cornell-Dubilier Electric Corp, South Plainfield, NJ, 1938.

[24] Georgiev, Alexander M., The Electrolytic Capacitor. Murray Hill Books, New York, 1945.

[25] Ginsberg, Gerald L., A User's Guide to Selecting Electronic Components. New York: John Wiley & Sons, 1981.

[26] Goedbloed, Jasper, Electromagnetic Compatibility. Prentice-Hall, New York, 1990.

[27] Gore, Gregory V., The Engineer's Master Guide to EMI Control . West Conshohocken, PA: R & B Enterprises, 1986.

[28] Graf, Rudolf F., Electronic Databook, 3rd Edition. Blue Ridge Summit: TAB Books, 1983.

[29] Hall, Stephen H., Hall, Garrett W., and McCall, James A., High-Speed Digital System Design, John Wiley & Sons, New York, 2000.

[30] Harper, Charles A., High Performance Printed Circuit Boards . New York: McGraw-Hill, 2000.

[31] Hartal, Oren, Electromagnetic Compatibility by Design, 4th Edition. West Conshohocken, PA: R & B Enterprizes, 1996.

[32] Hartley, Rick, High Speed Design: A Practical Approach. IPC.

[33] Hayward, Wes, Campbell, Rick, and Larkin, Bob, Experimental Methods in RF Design. Newington, CT: ARRL, 2003.

[34] Johnson, Howard and Graham, Martin, High-Speed Digital Design. Prentice- Hall, Upper Saddle River, NJ, 1993.

[35] Keenan, R. Kenneth, Decoupling and Layout of Digital Printed Circuits. TKC, Pinellas Park, FL, 1985.

[36] Keenan, R. Kenneth, Digital Design for Interference Specifications. TKC, Pinellas Park, FL, 1983.

[37] Keenan, R. Kenneth, FCC/VDE Noise Specifications: Application of Ferrite Beads to Decoupling Printed-Circuit Boards from Backplanes. Pinellas Park, FL: The Keenan Corporation, 1984.

[38] Lenk, John D., Handbook of Simplified Solid-State Circuit Design . Englewood Cliffs, NJ: Prentice-Hall, 1971.

[39] Lenk, John D., Manual for Integrated Circuit Users. Reston, VA: Reston Publishing, 1973.

[40] Lund, Preben, Generation of Precision Artwork for Printed Circuit Boards. New York: John Wiley & Sons, 1978.

[41] Lund, Preben, Printed Circuit Board Precision Artwork Generation and Manufacturing Methods. Westlake Village, CA: Bishop Graphics, 1986.

[42] Mancini, Ron, Op Amps for Everyone, 2nd Edition. New York: Newnes, 2003.

[43] Marcoux, Phil P., Surface Mount Technology: Design for Manufacturability. Dearborn, MI: SME, 1989.

[44] Mardiguian, Michel, Controlling Radiated Emissions by Design 2nd ed., Kluwer, Boston, 2001.

[45] Mardiguian, Michel, Cookbook of EMI Fixes. Gainesville, VA: ICT, 1989.

[46] Mardiguian, Michel, Electromagnetic Control in Components and Devices. Gainesville, VA: Interference Control Technologies, 1988.

[47] Mardiguian, Michel, Interference Control in Computers and Microprocessor- Based Equipment. Don White Consultants, Gainesville, VA, 1984.

[48] Mills, Jeffrey P., Electromagnetic Interference Reduction in Electronic Systems. Englewood Cliffs, NJ: PTR Prentice Hall, 1993.

[49] Montrose, Mark I., EMC and the Printed Circuit Board. IEEE Press, New York, 1999.

[50] Montrose, Mark I., Printed Circuit Board Design Techniques for EMC Compliance. IEEE Press, New York, 1996.

[51] Morris, Robert L., and Miller, John R., Designing with TTL Integrated Circuits. New York: McGraw-Hill, 1971.

[52] Morrison, Ralph, Solving Interference Problems in Electronics . New York: John Wiley & Sons, 1995.

[53] Norris, Bryan, Digital Integrated Circuits and Operational-Amplifier and Optoelectronic Circuit Design. New York: McGraw-Hill, 1976.

[54] Novak, Istvan, and Miller, Jason R., Frequency-Domain Characterization of Power Distribution Networks. Boston, MA: Artech House, 2007.

[55] Novak, Istvan, Power Distribution Network Design Methodologies . Chicago, IL: International Engineering Consortium, 2008.

[56] O'Hara, Martin, EMC at Component and PCB Level. Boston, MA: Newnes, 1998.

[57] Ott, Henry W., Noise Reduction Techniques in Electronic Systems, 2nd Edition. New York: John Wiley & Sons, 1988.

[58] Ott, Henry W., Noise Reduction Techniques in Electronic Systems. John Wiley & Sons, New York, 1976.

[59] Paul, Clayton R., Introduction to Electromagnetic Compatibility , John Wiley & Sons, New York, 1992.

[60] Poon, Ron K., Computer Circuits Electrical Design, Prentice Hall, Englewood Cliffs, NJ, 1995.

[61] Ritchey, Lee W., Right the First Time: A Practical Hand Book on High Speed PCB and System Design, Volume 1. Speeding Edge, 2003.

[62] Ritchey, Lee W., Right the First Time: A Practical Handbook on High Speed PCB and System Design, Volume 2. Speeding Edge, 2006.

[63] Ritenour, Bill, and White, Donald, EMI Control in Computers & Microprocessor-Based Equipment. NTU: 1992.

[64] Scarlett, J. A., Transistor-Transistor Logic and Its Interconnections. New York: Van Nostrand Reinhold, 1972.

[65] Sheingold, Daniel H., Transducer Interfacing Handbook: A Guide to Analog Signal Conditioning. Norwood, MA: Analog Devices, 1981.

[66] Shoji, Masakazu, High-Speed Digital Circuits. Reading, MA: Addison-Wesley, 1996.

[67] Smith, Douglas C., High Frequency Measurements and Noise in Electronic Circuits. Van Nostrand Reinhold, New York, 1993.

[68] Stout, David F., and Kaufman, Milton, Handbook of Operational Amplifier Circuit Design. New York: McGraw-Hill, 1976.

[69] Tummala, Rao R., Fundamentals of Microsystems Packaging. New York: McGraw-Hill, 2001.

[70] Ulrich, Richard K., and Schaper, Leonard W., Integrated Passive Component Technology. Piscataway, NJ: IEEE Press, 2003.

[71] Violette, J. L. Norman, White, Donald R. J., and Violette, Michael F., Electromagnetic Compatibility Handbook. New York: Van Nostrand Reinhold, 1987.

[72] Violette, J. L. Norman, Noise Control & Design Considerations in High Performance Electronic Circuits & Systems. Falls Church, VA: Violette Engineering, 1993.

[73] White, Donald R. J., EMI Control in the Design of Printed Circuit Boards and Backplanes. Gainesville, VA: Don White Consultants, 1981.

[74] Williams, Tim, EMC for Product Designers 2nd ed., Newnes, Woburn, MA, 1996.

[75] Young, Brian, Digital Signal Integrity, Prentice Hall, Upper Saddle River, NJ, 2001.

THESES:

[76] Choi, Myoung Joon, Efficient Broadband Electromagnetic Modeling of the Power Distribution Network in High-Speed, Mixed-Signal Integrated Circuits. Ph. D. Thesis for University of Illinois at Urbana-Champaign, Urbana-Champaign, IL, 2004.

[76d] Mandrekar, Rohan, Modeling and Co-simulation of Signal Distribution and Power Delivery in Packaged Digital Systems. Ph. D. Thesis for Georgia Institute of Technology, Atlanta, GA, May 2006.

[76h] Muthana, Prathap K., Design of High Speed Packages and Boards Using Embedded Decoupling Capacitors, Ph. D. Thesis for Georgia Institute of Technology, Atlanta, GA, 2007.

[76l] Na, Nanju, Modeling and Simulation of Planes in Electronic Packages. Ph. D. Thesis for Georgia Institute of Technology, Atlanta, GA, Jan. 2001.

[76p] Selli, Giuseppe, BGA Footprints Modeling and Physics Based Via Models Validation for Power and signal Integrity Applications. Ph. D. Thesis for University of Missouri - Rolla, Rolla, MS, 2007.

[77] Wang, Wei, Parameter Extraction for Electronic Packaging and Decoupling Methodology for Power Delivery Systems. Ph. D. Thesis for University of California, Santa Cruz, CA, Sept. 2003.

PAPERS, APPLICATION NOTES, MAGAZINE ARTICLES, REPORTS, AND WEB PAGES:

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[79] "8 Hints for Successful Impedance Measurements," Hewlett-Packard Application Note 346-4.

[80] "8088 8-bit HMOS Microprocessor 8088/8088-2," Intel, Aug. 1990.

[81] "A High Frequency Broadband Filter," Microwave Journal, Sept. 15, 2003.

[82] "A Review of the Literature."

[83] "Above Board," UltraCAD.

[84] "Advances in Surface Mount Filtering Technology," Syfer.

[85] "AMD-K6(R) Processor EMI Design Considerations," AMD Application Note 22023, Mar. 1999.

[86] "AMD-K6(R) Processor Power Supply Design," AMD Application Note 21103, Feb. 1999.

[87] "Application Suggestions for X2Y Technology," X2Y.

[88] "AVX Dielectric Comparison Chart," AVX.

[89] "AVX's OxiCap(TM) Niobium Oxide Capacitors Deliver Cost Effective, Lead-Free Non-Burning High Capacitance Performance," AVX.

[90] "Best Board Design Practices for the Power Distribution Network (PDN)," Altera, 2006.

[91] "Buried Capacitance," Merix.

[92] "Buried Capacitance Design Guide," Zycon, 1995.

[93] "Buried Capacitance(TM) A Simple Solution," Zycon.

[94] "Bypass Capacitor Selection for High-Speed Designs," Micron Technical Note TN-00-06, Sept. 1999.

[95] "Capacitance Without Capacitors," Hadco, Nov. 23, 1998.

[96] "Capacitor ESR Measurement Techniques," American Technical Ceramics.

[97] "Careful Design Helps Exorcise Noise Demons From PC Audio," Aug. 21, 2000.

[98] "Ceramic Capacitors," Murata.

[99] "Circuit designing cautions (OS-CON)," Sanyo.

[100] "CMOS Power Consumption and Cpd Calculation," Texas Instruments Application Note SCAA035B, June 1997.

[101] "CMOS, the Ideal Logic Family," Fairchild Semiconductor Application Note 77, Jan. 1983.

[102] "Comparative Device-Only Measurements of X2Y, Arrays and Ordinary Capacitors," X2Y, Feb. 24, 2006.

[103] "Comparison Testing, A Single X2Y Components vs. Three Standard Bulk Capacitors (1) X and (2) Y's, Line to Line testing, Both DUT's Referenced to ground," X2Y.

[104] "Comparison Testing, A Single X2Y Component vs. Three Standard Capacitors (1) X and (2) Y's, Line to Ground and Line to Line Testing," X2Y.

[105] "Construction and Characteristics of OS-CON," Sanyo.

[106] "Crucial Precautions (OS-CON)," Sanyo.

[107] "DC-To-DC Converters using X2Y Technology," X2Y Note# 2009, V3.0, Apr. 28, 2005.

[108] DESIGNERCOUNCIL archives. [109] "Design Considerations," Fairchild Semiconductor, Nov. 1999.

[110] "Design Considerations for Class-D Audio Power Amplifiers," Texas Instruments Application Report SLOA031, Aug. 1999.

[111] "Design Engineers Battle The Dark Side Of Electromagnetism," Dec. 18, 2000.

[112] "Design for EMI," Intel Application Note AP-589, Feb. 1999.

[113] "Designing Fast Response Synchronous Buck Regulators Using the TPS5210," Texas Instruments Application Report SLVA044, Mar. 1999.

[114] "Designing for EMI Compliance - Part 1 Design of the PC Board," 1985-86 Compliance Engineering, 1985, pp. 87-88, 97-110.

[115] "Designing the Input Filter for a Pentium II Processor Converter," Fairchild Application Bulletin AB-16.

[116] "Designing with TTL," Fairchild Semiconductor Application Note 363, June 1984.

[117] "Details of Output Capacitor Selection for Pentium II Process Converters using the RC5051," Fairchild Application Bulletin AB-14.

[118] "Do passive components degrade audio quality in your portable device?," Maxim Engineering Journal, vol. 48, pp. 16-19.

[119] "EEE Parts Derating," NASA Practice no. PD-ED-1201.

[120] "Electromagnetic Analysis of Decoupling Capacitor Mounting Structures with Sembeor," Simbeor Applications Note #2008_01, Mar. 2008.

[121] "ELNA Chip Aluminum Electrolytic Capacitors Technical Data,"

[122] "Embedded IntelDX2(TM) Processor," Intel, Dec. 1997,

[123] "EMC Improvement Guidelines," Atmel Application Note, Rev. 4279B-8051-08/03, Aug. 2003.

[124] "ESR Loss Factors," American Technical Ceramics.

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[126] "Film Capacitors Precautions and Guidelines," Nippon Chemi-con.

[127] "Flexible Motherboard Power Distribution and Control for the Pentium(R) III Xeon Processor," Intel Application Note AP-933, Jan. 2000.

[128] "Follow PC-Board Design Guidelines for Lowest CMOS EMI Radiation," Fairchild Semiconductor Application Note 389, Jan. 1985.

[129] "Frequency Characteristics of OS-CON," Sanyo.

[130] "General Routing Techniques with Emphasis on PI6C10X Clocks," Pericom Application Note 8.

[131] "Generating PSpice models for X2Y capacitors from S-parameters," Phycomp Application Note, Jan. 2003.

[132] "Get the Most from X2Y Capacitors with Proper Attachment Techniques," X2Y Application Note 3008, V1, 2/23/06.

[133] "Guidelines for Printed Circuit Board Design," United Chemi-con.

[134] "HC-MOS Power Dissipation," Fairchild Semiconductor Application Note 303.

[135] "High-Speed Board Design Advisor: Power Distribution Network," Altera Tecnical Brief TB-092-1.0, Ver. 1.0, Nov. 2007.

[136] "High-Speed-CMOS designs address noise and I/O levels," Fairchild Semiconductor Application Note 375, Oct, 1984.

[137] "High Speed Decoupling Strategy," Hadco, June 23, 1998.

[138] "IBM PowerPC 440GP Embedded Processor PowerPC 440GP System Design Considerations," IBM Application Note.

[139] "Implementation Guidelines for 3.3V Pentium(R) Processors with VRE Specifications for Desktop and Server Designs," Intel Application Note AP-522, June 1997.

[140] "Implementing the RC5040 and RC5042 DC-DC Converters on Pentium(R) Pro Motherboards," Fairchild Application Note 42.

[141] "Implementing the RC5050 and RC5051 DC-DC Converters on Pentium(R) Pro Motherboards," Fairchild Application Note 50.

[142] "Intel386(TM) DX Microprocessor 32-bit CHMOS Microprocessor with Integrated Memory Management," Intel, Dec. 1995.

[143] "Intel486(TM) Processor Family Decoupling Recommendations," Intel.

[144] "Layout and Termination Techniques for Cypress Clock Generators," Cypress.

[145] "Layout Guidelines for the TPA300x Series Parts," Texas Instruments Application Report SLOA103, July 2003.

[146] "Less Noise in High Frequency Circuits."

[147] "Line Driving and System Design," National Semiconductor Application Note 991.

[148] "Logic-System Design Techniques Reduce Switching-CMOS Power," Fairchild Semiconductor Application Note 376, Oct. 1984.

[149] "Low Inductance Chip Capacitors," AVX.

[150] "Low Inductance Chip Capacitors," AVX.

[151] "Low Inductance Chip Capacitors," AVX.

[152] "M80C286 High Performance CHMOS Microprocessor with Memory Management and Protection," Intel, Feb. 1990.

[153] "Maintaining Clean Power," UltraCad.

[154] "Measurement and Comparative S21 Performance of Raw and Mounted Decoupling Capacitors," X2Y Note# 3006, V2, Apr. 24, 2007.

[155] "Microwave Datamate," IFR.

[156] "Mobile AMD-K6(R) Processor Power Supply Design," AMD Application Note 22495, May 1999.

[157] "Mounting precautions (OS-CON)," Sanyo.

[158] "Multilayer Ceramic Capacitors Precautions and Guidelines," Nippon Chemi-con.

[159] "Multilayer Ceramic EMI Filters," Syfer.

[160] "New and Lower ESR Capabilities in Polymer Products," Arrow Asian Times, July 2003.

[161] "News: CMC Replacements for Tantalum Capacitors."

[162] "Novacap Technical Brochure."

[163] "Omni Review," Omni Graphics, 2000.

[164] "Optimize Power Distribution Analysis In High-Speed System Designs," Nov. 20, 2000.

[165] "Oscilloscope Probing of PC133/Rambus Circuits," Pericom Application Note 21.

[166] "Panasonic Specialty Polymer Aluminum Electrolytic Capacitors (SP CAP)."

[167] "PCB Design Guidelines for Reduced EMI," Texas Instruments SZZA009, Nov. 1999.

[168] "Pentium(R) II Processor at 350MHz, 400MHz, and 450MHz," Intel, Aug. 1998.

[169] "Pentium(R) III Processor for the PGA370 Socket at 500MHz to 866MHz," Intel, Mar. 2000.

[170] "Pentium(R) III Processor Power Distribution Guidelines," Intel Application Note, Apr. 1999.

[171] "Pentium(R) III Xeon(TM) Processor Power Distribution Guidelines," Intel Application Note AP-912, Mar. 1999.

[172] "Pentium(R) Pro Family Developer's Manual, Volume 1: Specifications," Intel, 1996.

[173] "Pentium(R) Pro Processor Power Distribution Guidelines," Intel Application Note AP-523, Nov. 1995.

[174] "Pentium Processor," Intel, June 1997.

[175] "Pentium Processor Flexible Motherboard Design Guidelines," Intel Application Note AP-579, June 1997.

[176] "Pentium Processor with MMX(TM) Technology," Intel, June 1997.

[177] "Pentium(R) Processor With Voltage Reduction Technology: Power Supply Design Considerations for Mobile Systems," Intel Application Note AP-519, June 1997.

[178] "Perfect Timing A Design Guide for Clock Generation and Distribution," Cypress Semiconductor, 2002.

[179] "Piezoelectric Effect in Ceramic Capacitors," American Technical Ceramics.

[180] "Planning for High Speed XC9500XL Designs," Xilinx Application Note XAPP115, Sept. 28, 1998.

[181] "Planning for High Speed XC9500XV Designs," Xilinx Application Note XAPP361, Aug. 8, 2001.

[182] "Power Dissipation in High-Performance ASICs."

[183] "Power Integrity and Ground Bounce Simulation of High Speed PCBs," Ansoft Presentation #11.

[184] "Power Intel's Pentium II Microprocessor using the SC1151CS and the MP60F VRM," Semtech Application Note AN97-1, Mar. 11, 1998.

[185] "Power Supplies for Pentium(TM), PowerPC(TM), and Beyond," Maxim, 2000.

[186] "PowerPC 405GP System Design Considerations," IBM PowerPC Application Note, Feb. 21, 2001.

[187] "PowerPC 750 Design Guidelines," IBM PowerPC Applications Note.

[188] "PowerPC Embedded Processors PowerPC 740/750: Power Notes," IBM Application Note.

[189] "PowerPC Embedded Processors PowerPC 750CXe Family: Power Notes," IBM Application Note.

[190] "Powering Portable CPU Cores," Maxim, 2000.

[191] "Precautions and Guidelines," Nippon Chemi-con.

[192] "Precautions and guidelines for users (OS-CON)," Nippon Chemi-con.

[193] "Precautions and guidelines for users (Tantalum)," Nippon Chemi-con.

[194] "Precautions and Guidelines to Users for Aluminum Electrolytic Capacitors -Index-," Chemi-con.

[195] "Precautions and Guidelines to Users for Multilayer Ceramic Capacitors," Nippon Chemi-con.

[196] "Precautions and Guidelines to Users for Tantalum Electroytic Capacitors," Nippon Chemi-con.

[197] "Precautions in Using Tantalum Capacitors."

[198] "Precautions when using OS-CONs in circuits," Sanyo.

[199] "Preferred Laminates and Prepreg - Materials Properties Comparison," Merix.

[200] "Printed-Circuit-Board Layout for Improved Electromagnetic Compatibility," Texas Instruments SDYA011, Oct. 1996.

[201] "Processor Hall of Fame."

[202] "Protection, Decoupling, and Filtering of Cypress CMOS Circuits," Cypress.

[203] "Reliability Issues."

[204] "Sanyo Frequency Characteristics of OS-CON."

[205] "Sanyo OS-CON ESR Matrix Table."

[206] "SC1154 Hysteretic Controller," Semtech Application Note AN99-6, Mar. 1, 2000.

[207] "Selecting RF Chip Capacitors for Wireless Applications," American Technical Ceramics.

[208] "Shunt Measurement, (1) X2Y vs. (2) Standard Capacitors," X2Y.

[209] "Shunt Measurement X2Y Standard Capacitors," X2Y, Sept. 27, 2003.

[210] "Slot 1 Processor Power Distribution Guidelines," Intel Application Note AP-587, May 1997.

[211] "Solutions to Current High-Speed Board Design," Pericom Application Note 22.

[212] "SP Capacitor Q & A," Panasonic.

[213] "SRAM System Design Guidelines," Cypress Semiconductor, Oct. 25, 2002.

[214] "System design and layout techniques for noise reduction in MCU-based systems," Microprocessors and Microsystems, vol. 20, pp. 303-309, 1996.

[215] "System Power Board Distribution Guidelines for PID9q-604e(TM) (Mach 5)," IBM Application Note AN-022, Sept. 1997.

[216] "Tantalum Capacitors With Solid Electrolyte (Chip Type)," Mectron.

[217] "Tantalum Solid Electrolytic Capacitors Precautions and Guidelines," Nippon Chemi-Con.

[218] "Technical Notes on Aluminum Electrolytic Capacitors," Nichicon Cat. 8101C, June 1999.

[219] "The Buried Capacitance(TM) Design Guide," Hadco 95-06-001, 1995.

[220] "The Bypass Capacitor in High-Speed Environments," Texas Instruments SCBA007A, Nov. 1996.

[221] "The Facts about the Input Impedance of Power and Ground Planes," Sigrity.

[222] "The Feedthrough Varistor a New Weapon Against EMI,"

[222d] "There Was Prior Art, ZBC Inventor Says," Printed Circuit Design and Manufacture, vol. 20 no. 11, pp. 10,47, Nov. 2003.

[223] "Third Generation Power Conversion Solution for Pentium(R) II Motherboards," Fairchild Application Note 57.

[224] "Type ESRE Surface Mount Polymer Aluminum Electrolytic Capacitors."

[225] "Ultra-Low Impedance Measurements Using 2-Port Measurements," Agilent Technologies Application Note.

[226] "Understanding Aluminum Electrolytic Capacitors," United Chemi-con,

[227] "Understanding Buck Power Stages in Switchmode Power Supplies," Texas Instruments Application Report SLVA057, Mar. 1999.

[228] "Understanding Capacitor Inductance and Measurement in Power Bypass Applications," X2Y Note# 3009, V1, Feb. 27, 2006.

[229] "Unitrode Power Supply Design Seminar, SEM-1100," Unitrode, 1996.

[230] "Using a Spatial View to Understand and Solve Common Power Bypass Problems," Teraspeed Consulting Group, 2008.

[231] "Using Decoupling Capacitors," Cypress.

[232] "Vertical Orientation of ATC Chip Capacitors on Striplines," American Technical Ceramics.

[233] "Voltage Guidelines for Pentium Processors with MMX Technology," Intel Application Note AP-580, June 1997.

[234] "Voltage Regulator-Down (VRD) 10.0," Intel 252885-001, Apr. 2003.

[235] "Voltage Regulator-Down (VRD) 11.0," Intel, Nov. 2006.

[236] "VRM 8.1 DC-DC Converter Design Guidelines," Intel 243408-001, May 1997.

[237] "VRM 8.2 DC-DC Converter Design Guidelines," Intel 243773-002, Mar. 1999.

[238] "VRM 8.3 DC-DC Converter Design Guidelines," Intel 243870-004, Mar. 2000.

[239] "VRM 8.4 DC-DC Converter Design Guidelines," Intel 245335-001, Nov. 1999.

[240] "VRM 8.5 DC-DC converter Design Guidelines," Intel 249659-002, Mar. 2002.

[241] "VRM 9.0 DC-DC Converter Design Guidelines," Intel 249205-004, April 2002.

[242] "VRM 9.1 DC-DC Converter Design Guidelines," Intel 298646-001, January 2002.

[243] "X2Y Capacitors in IC Back-Side Mounting Applications," X2Y Note# 3010, V1, Oct. 25, 2006.

[244] "X2Y Comparative Decoupling Performance in 4 Layer PCBs," X2Y.

[245] "X2Y Inductance Ratings," X2Y Note# 3013, V1, Sept. 9, 2008.

[246] "X2Y Live FPGA Power Bypass,", X2Y Attenuators, Jan. 25, 2006.

[247] "X2Y Technology: Component Grounding," Application Note 7032001-1.

[248] "X2Y Technology Presentation," X2Y, Oct. 20, 2003.

[249] Abothu, Isaac Robin, Raj, P. Markondeya, Balaraman, Devarajan, Govind, Vinu, Bhattacharya, Swapan, Sacks, Michael D., Swaminathan, M., Lance, Michael J., and Tummala, Rao, "Development of High-k Embedded capacitors on Printing Wiring Board Using Sol-Gel and Foil Transfer Processes," 54th Electronic Components & Technology Conference, Volume 1, Las Vegas, NV, June 1-4, 2004, pp. 514-520.

[249d] Abothu, Isaac Robin, Raj, P. Markondeya, Balaraman, Devarajan, Sacks, Michael D., Bhattacharya, Swapan, and Tummala, Rao R., "Low-Cost Embedded Capacitor Technology With Hydrothermal and Sol-Gel Processes," 2004 9th International Symposium on Advanced Packaging Materials, Atlanta, GA, Mar. 24-26, 2004, pp. 78-83.

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[835h] Jiang, Rongrong, Huang, Tao, Tang, Yang, Liu, Jiali, Xue, Leigang, Zhuang, Jihua, and Yu, Aishui, "Factors influencing MnO2/multi-walled carbon nanotubes composite's electrochemical performance as supercapacitor electrode," Electrochimica Acta, vol. 54 no. 27, pp. 7173-7179, Nov. 30, 2009.

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[839] Johnson, Howard, "ADC Grounding," EDN, vol. 45, no. 25, pp. , Dec. 7, 2000.

[840] Johnson, Howard, "Another Version of a Coax Probe," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 18.

[841] Johnson, Howard, "Benefits of Resistive Probe," High-Speed Digital Design On-Line Newsletter, vol. 5, issue 4.

[842] Johnson, Howard, "Bypass Array Model," High-Speed Digital Design On-Line Newsletter, vol. 6, issue 2.

[843] Johnson, Howard, "Bypass Arrays," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 6.

[844] Johnson, Howard, "Bypass Capacitor Layout," Printed Circuit Design, vol. 14, no. 8, pp. , Aug. 1997.

[845] Johnson, Howard, "Bypass Capacitor Layout," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 3.

[846] Johnson, Howard, "Bypass Capacitor Sequencing," High-Speed Digital Design On-Line Newsletter, vol. 9 issue 7.

[847] Johnson, Howard, "Bypass Multi-Valued Arrays," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 17.

[848] Johnson, Howard, "Capacitor Layout Matters," EDN, Sept. 5, 2002.

[849] Johnson, Howard, "Capacitor Placement," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 1.

[850] Johnson, Howard, "Clean Power," EDN, vol. 45, no. 16, pp. 32, Aug. 3, 2000.

[851] Johnson, Howard, "Dielectric Loss Tangents," High-Speed Digital Design On-Line Newsletter, vol. 4 issue 5.

[852] Johnson, Howard, "Earth Ground," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 12.

[853] Johnson, Howard, "EMC/Signal Integrity for High-Speed Digital Circuits," Aug 2, 1999.

[854] Johnson, Howard, "Equivalent Circuit Source Impedance," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 9.

[855] Johnson, Howard, "ESR or regulator output capacitor," High-Speed Digital Design On-Line Newsletter, vol. 5, issue 3.

[856] Johnson, Howard, "Front-connected power supply," High-Speed Digital Design On-Line Newsletter, vol. 4, issue 17.

[857] Johnson, Howard, "Ground Currents," High-Speed Digital Design On-Line Newsletter, vol. 3, issue 7.

[858] Johnson, Howard, "Ground/Power Planes," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 8.

[859] Johnson, Howard, "Healthy Power," EDN, vol. 45, no. 7, pp. 32, Mar. 30, 2000.

[860] Johnson, Howard, "High-Speed Return Signals," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 15.

[861] Johnson, Howard, "Improving Bypass Capacitor Layout." Printed Circuit Design, vol. 14, no. 9, pp. 27-28, Sept. 1997.

[862] Johnson, Howard, "Interplane Capacitance," High-Speed Digital Design On-Line Newsletter, vol. 3, issue 21.

[863] Johnson, Howard, "Measuring Droop," EDN, vol. xx no. x, pp. xx-xx, Feb. 3, 2005.

[864] Johnson, Howard, "Measuring Power and Ground," High-Speed Digital Design On-Line Newsletter, vol. 3, issue 13.

[865] Johnson, Howard, "Measuring Power Ground Impedance," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 14.

[866] Johnson, Howard, "Measuring Power Plane Resonance," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 27.

[867] Johnson, Howard, "Moats and Floats," Electronic Design, vol. 45, no. 4, pp. 181, Feb. 17, 1997.

[868] Johnson, Howard, "Multiple ADC Grounding," EDN, vol 46, no. 3, pp. 30, Feb. 1, 2001.

[869] Johnson, Howard, "Mutual Understanding," EDN, vol. 43, no. 1, pp. 24, Jan. 1, 1998.

[870] Johnson, Howard, "On Chip Bypassing with End Terminations," EDN, vol. xx no. x, pp. xx-xx, May 27, 2004.

[871] Johnson, Howard, "Operating Above Resonance," Electronic Design, vol. 45, no. x, pp. xx-xx, Apr. 14, 1997.

[872] Johnson, Howard, "Parasitic inductance of a bypass capacitor," EDN, vol. 45, no. 15, pp. 32, July 20, 2000.

[873] Johnson, Howard, "Parasitic Inductance of Bypass Capacitor II," High-Speed Digital Design On-Line Newsletter, vol. 6, issue 9.

[874] Johnson, Howard, "Picket Fences," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 16.

[875] Johnson, Howard, "Power and Ground Source Impedance," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 4.

[876] Johnson, Howard, "Power Bus Noise," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 9.

[877] Johnson, Howard, "Power Plane Resistance," EDN, July 11, 2002.

[878] Johnson, Howard, "Power Plane Resonance," EDN, vol. 43, no. 18, pp. 22, Sept. 1, 1998.

[879] Johnson, Howard, "Probes," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 13.

[880] Johnson, Howard, "Probing for Noise," EDN, vol. 42, no. 25, pp. 215, Dec. 4, 1997.

[881] Johnson, Howard, "Probing High-Speed Digital Designs," Electronic Design, vol. 45, no. 6, pp. 155-162, Mar 12, 1997.

[882] Johnson, Howard, "Quality Factor," EDN, vol. 50 no. 25, pp. 38, Dec. 5, 2005.

[883] Johnson, Howard, "Radiated Digital Ground Noise," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 17.

[884] Johnson, Howard, "Resistance," High-Speed Digital Design On-Line Newsletter, vol. 1, issue 11.

[885] Johnson, Howard, "Segmenting the Vcc Plane," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 18.

[886] Johnson, Howard, "Short-Term Impedance of Planes," High-Speed Digital Design On-Line Newsletter, vol. 6 issue 5.

[887] Johnson, Howard, "Single Point Ground," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 26.

[888] Johnson, Howard, "Steel-plated power planes," EDN, vol. 47, no. 6, pp. 26, Mar. 21, 2002.

[889] Johnson, Howard, "TDR and Ice Cube Trays," High-Speed Digital Design On-Line Newsletter, vol. 3, issue 5.

[890] Johnson, Howard, "Ten Layer Stack," High-Speed Digital Design On-Line Newsletter, vol. 2, issue 11.

[891] Johnson, Howard, "The Way Home," EDN, vol. 45, no. 13, pp. 32, June 22, 2000.

[892] Johnson, Howard, "Through-hole clearances," EDN, vol. 44, no. 14, pp. , July 8, 1999.

[893] Johnson, Howard, "Trace Between Capacitors," High-Speed Digital Design On-Line Newsletter, vol. 3, issue 4.

[894] Johnson, Howard, "Voltage-Regulator Droop," EDN, vol. xx no. x, pp. xx-xx, Sept. 14, 2006.

[895] Johnson, Howard, "Voltage-Regulator Model," EDN, vol. xx no. x, pp. xx-xx, Aug. 17, 2006.

[896] Johnson, Howard, "VRM Stability - Part I: Feedback," High-Speed Digital Design On-Line Newsletter, vol. 10 issue 3.

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[899] Jung, Sung Man, Bae, In Sung, Yoon, Jae Sik, Goto, Shoji, and Kim, Byung Il, "Evaluation of Electric Properties for Niobium Capacitors," Materials Transactions, vol. 48 no. 12, pp. 3197-3200, Dec. 2007.

[899d] Juodkazis, K., Juodkazyte, J., Sukiene, V., Griguceviciene, A., and Selskis, A., "On the charge storage mechanism at RuO2/0.5 M H2SO4 interface," Journal of Solid State Electrochemistry, vol. 12 no. 11, pp. 1399-1404, Nov. 2008.

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[901] Kagata, Makoto, and Abe, Yutaka, "Dielectric Properties of Sintered TiO2 and TiO2-WO3 Mixtures," 2006 CARTS Conference Proceedings, Orlando, FL, Apr. 3-6, 2006, pp. xx-xx.

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[903] Kahng, Sungtek, "Characteristics of the Resonance and Impedance of Power-Bus Structure with the Embedded Metamaterial Substrate," Electrical Design of Advanced Packaging and Systems Symposium, Seoul, Korea, Dec. 10-12, 2008, pp. 16-19.

[904] Kahng, Sungtek, and Choi, Jaehoon, "Correlated effects of decoupling capacitors and vias loaded in the PCB power-bus," IEEE Antennas and Propagation Society International Symposium 2006, Albuquerque, NM, July 9-14, 2006, pp. 77-80.

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